The invention relates a method and an apparatus for generating test patterns used in testing a semiconductor integrated circuit, and in particular, to a method and an apparatus for generating test patterns which are used to detect a gate delay fault, an open fault which gives rise to a gate delay fault, and a path delay fault with the aid of a transient power supply current signal.
Test patterns for testing an abnormal delay time of a logic gate in a semiconductor integrated circuit under test (hereafter referred to as “gate delay fault”) are provided in the prior art by preparing a test pattern which initializes an output from a logic gate under test of the circuit to a signal value (initial logic value) and another test pattern which tests the logic gate under test for a stuck-at fault, or a fault that the output from the logic gate under test is fixed to the initial logic value. FIG. 1a shows an example of the semiconductor circuit under test. The circuit includes input terminals x2 and x3 connected to inputs of NAND gate G1. Input terminals x3 and x4 are connected to inputs of NAND gate G2. Outputs from NAND gates G1 and G2 feed NOR gate G3, the output of which feeds NOR gate G4 together with an input applied to an input terminal x1. Output from NAND gate G3 also feeds NAND gate G5 together with an input applied to an input terminal x5. Outputs from NOR gate G4 and NAND gate G5 feed NOR gate G6, the output of which is connected to an output terminal z1.
For the illustrated semiconductor circuit under test, a test pattern which examines a “slow-to-rise” gate delay fault of the logic gate G3 is generated in a manner as described below. First of all, a test pattern x1=x, x2=x, x3=0, x4=x and x5=x which produces an initial value of “0” at the output of the faulty gate G3 is determined as shown in FIG. 1a. Here, “x” indicates a “don't care” value or either “1” or “0”. This test pattern is denoted hereafter as v1=(xx0xx). Assuming a stuck-at fault at the faulty gate G3 such that its output is fixed to the initial value of “0”, a test pattern v2=(0x111) is then determined which allows the stuck-at fault to be detected at the output signal line of the semiconductor circuit (see FIG. 1(b)). As a consequence, a test pattern sequence which detects a slow-to-rise fault at gate G3 is defined as T=<v1, v2>=<“xx0xx”, “0x111”>. A technique for generating test patterns for the gate delay fault is disclosed, for example, in E. S. Park and M. R. Mercer, “An Efficient Delay Test Generation System for Combinatorial Logic Circuits”, Transactions on Computer-Aided Design, 11(7), pp 926-938, 1992 or U. Mahlstedt, “DELTEST: Deterministic Test Generation for Gate Delay Faults”, Proceedings of IEEE International Test Conference, pp. 972-980, 1993.
A signal propagation path in a semiconductor integrated circuit is referred as a path. A time interval required for a signal to propagate from an input signal line to an output signal line of a path is referred to as a path delay time. When a path delay time exceeds a given value, a circuit fails to operate normally, and this is referred as a path delay fault. Two test patterns are generally necessary to test a delay fault, and are commonly referred to as a test vector pair or a test pattern sequence. According to the conventional practice, a test pattern sequence which tests a path delay fault in an integrated circuit is generated by utilizing a five logic value system shown in FIG. 2 and assigning the logic values to various signal lines in the circuit under test according to an implication table shown in FIG. 3 or a sensitizing table shown in FIG. 4. In FIG. 2, S0 remains to be “0” for either pattern v1 or v2; S1 remains to be “1” for either pattern v1 or v2; U0 is equal to “x” for pattern v1 and to “0” for pattern v2; U1 is equal to “x” for pattern v1 and to “1” for pattern v2; and XX remains to be “x” for either pattern v1 or v2.
Output states of AND gate shown in FIG. 3a1 when its input terminals x1, x2 assume various combinations of S0, U0, S1, U1 and XX are illustrated in the implication table of FIG. 3a2. To give an example, when x1 is equal to S0 and x2 is equal to U0, it follows that v1=<0,x> and v2=<0,0>, and thus the output is <0,0>=S0. Output states of NOR gate shown in FIG. 3b1 when its input terminals x1, x2 assume various combinations of S0, U0, S1, U1, and XX are illustrated in the implication table of FIG. 3b2. Similarly, output states of an inverter shown in FIG. 3c1 when a single input terminal x1 assumes one of S0, U0, S1, U1 and XX are illustrated in the implication table of FIG. 3c2.
FIG. 4a shows a value of the other input signal to change the output status or to activate the circuit when one input to AND gate has changed from “0” to “1”. In the present instance, it may be S1 or from “x” to “1”. For the instance of FIG. 4b where one input changes from “1” to “0”, the other input may be U1 or remain to be “1” in order to change the output state (or to activate the circuit). FIG. 4c shows the five value logic of the other input signal required to activate the respective gates when one input to AND gate, NAND gate, OR gate or NOR gate rises from “0” to “1” or falls from “1” to “0”.
In an integrated circuit shown in FIG. 5a, inputs from input terminals x1 and x2 feed AND gate G1; inputs from input terminals x3 and x4 feed OR gate G2; the input from the input terminal x1 feeds an inverter G3; an output from the inverter G3 and an input from an input terminal x5 feed AND gate G5; outputs from the gates G1 and G2 feed NOR gate G4; and outputs from the gates G4 and G5 feed OR gate G6. In order to generate a test pattern for a path delay fault which might occur on a path P shown in thick lines in this circuit or a path extending from the input terminal x3 through G2, G4 and G6 to an output line, transition signals as shown in FIG. 5a are initially provided on signal lines located on the path P under test, the sensitizing table shown in FIG. 4c is utilized to apply signal values which activate the gates G2, G6 to side inputs, namely, input signal lines to the logic gates G2, G6, but which are not disposed on the path P, as shown in FIG. 5b, and finally, signal values to be applied to individual input signal lines are determined on the basis of signal values which have been allotted in the manner mentioned above, using the implication table shown in FIG. 3, as illustrated in FIG. 6. In the example shown in FIGS. 5 and 6, the test pattern sequence which tests the path delay fault on the path P is determined as T=<v1, v2>=<“S0 XX U1 S0 U0”>=<“0x00x”, “0x100”>. A technique for generating test patterns for the path delay fault is disclosed, for example, in C. J. Lin and S. M. Reddy, “On Delay Fault Testing in Logic Circuits”, Transactions on Computer-Aided Design, CAD-6(5), pp 694-703, 1987 (referred to as literature 1) or K. T. Cheng, A. Kristic and H. C. Chen, “Generation of High Quality Tests for Robustly Untestable Path Delay Faults”, Transactions on Computers, 45(12), pp 1379-1392, 1996.
The method of generating test patterns described above with reference to FIG. 1 is subject to a restriction that the influence of a fault must be propagated to an output terminal (pin) of a circuit under test because the technique is based on the observation of a voltage signal on the output terminal (pin) of the circuit under test, and thus the generation of test patterns involves a difficulty. In particular, to test for a small gate delay fault in which an increment in the delay time is minimal or less than a clock period of the circuit under test, an output signal from a faulty gate must be propagated to the output terminal (pin) through a signal transmission path having a greatest delay time, and accordingly, it is very difficult to generate two test patterns (test vector pair or test pattern sequence) to activate the fault.
In a conventional method of generating test patterns, the need to propagate the influence of a gate delay fault and an open fault to the output signal line increases the probability that logic values on signal lines which are produced by the implication operation to generate path test patterns may become contradictory among logic values on signal lines, resulting in difficulties that the number of times that the set-up of signals must be retried (back-track) to generate test patterns increases and that it takes an increased length of time to generate test patterns.
Accordingly, there is a need for a method of generating test patterns which is capable of generating test pattern sequence easily and rapidly in order to test for a gate delay fault, or an open fault which gives rise to a gate delay fault in an integrated circuit.
The method of generating test patterns described above with reference to FIGS. 5 and 6 is subject to a restriction that non-controlling input values must be set up to side inputs or every input signal line, which is not disposed on a path under test, to each logic gate disposed on the path under test in order to activate the path under test, and another restriction that there must not be any hazard (whisker-like voltage pulse) on the path under test and side inputs in order to generate a test pattern sequence which is qualified to a robust path delay fault testing, that is, test results independent from the timing of an output voltage sampling. As a consequence of this, it is with a great difficulty to generate a test pattern sequence. In addition, the number of path delay faults for which the test pattern sequence cannot be generated increases, presenting a problem that the trouble shooting rate of the path delay faults is degraded. The non-controlling input value refers to a logic value which cannot determine an output of a logic gate uniquely. For example, a non-controlling input value for AND gate or NAND gate is a logic value of “1”, and a non-controlling input value for OR gate or NOR gate is a logic value of “0”.
Accordingly, there is a need for a method of generating test patterns which is capable of easily and efficiently generating test pattern sequence which can be used with the path delay faults of an integrated circuit.
It is an object of the invention to provide a test pattern generating method and apparatus which is capable of generating easily and efficiently test pattern sequence which can be used with a delay fault or an open fault within a semiconductor integrated circuit, by utilizing a highly observable transient power supply current (IDDT) testing technique which is capable of testing a transient phenomenon in a circuit.
It is another object of the invention to provide a test pattern generating method and apparatus which is capable of easily generating test pattern sequence which can be used with a path delay fault in a semiconductor integrated circuit and thus capable of providing an efficient test pattern sequence, by utilizing a highly observable transient power supply current (IDDT) testing technique which is capable of testing a transient phenomenon in a circuit.